The present invention relates to a method for forming totally self-aligned, small geometry CMOS integrated circuits having LDD (lightly doped source/drain) and self-aligned buried contacts. More particularly, the process sequence is defined so that the buried contacts are automatically aligned with the n.sup.+ and p.sup.+ source/drain regions, which are formed using a single lithographic mask, and n-type and p-type gates are provided for the respective n-channel and p-channel devices. Furthermore, the process sequence is designed so that a number of the steps serve dual or multiple purposes to provide the necessary structural features with minimum process complexity. The resulting CMOS integrated circuit is characterized by reduced minimum feature size, due in part to the self-aligned buried contacts, reduced Miller capacitance, and reduced short channel effects.
Historically, as the microelectronics industry has attempted to develop small geometry, highly dense MOS integrated circuit components, various structural and operational problems have combined to limit device performance and manufacturing yields and, thus, the achievable feature sizes and densities. Among the most difficult of the problems are those collectively called short channel effects, which include hot carrier injection into the gate oxide and/or substrate, source-drain punch through, reduced breakdown voltage and impact ionization. In hot carrier injection, for example, electrons are injected into the gate oxide by the high electric field created by the narrow channel region adjacent the drain and, as a consequence, alter the threshold voltage of the device. In addition to the short channel effects, overlap between the gate electrode and the source and drain results in parasitic capacitance between the diffusion region and the gate, known as Miller capacitance, which decreases high frequency response and operational speeds.
Small geometry MOS devices also incur electrical shorts between interconnecting conductors such as the electrical conductors which contact the gate, source and drain. In a widely used self-aligned contact approach, a refractory metal such as tungsten is selectively deposited over the polysilicon gate and the source-drain regions to form low resistance, self-aligned contacts between the interconnect lines and the source/drain/gate. However, because of the small VLSI feature sizes and the associated close spacing of the gate electrodes to the source/drain contact regions, the metal deposited in this manner can short the gate to the adjacent source/drain regions. Shorting can also occur between other conductors such as the polysilicon interconnect lines.
Thus, as channel lengths and other device dimensions are reduced in VLSI integrated circuits, new device structures such as LDD and gate electrode sidewall dielectric spacers have been developed to reduce short channel effects and to optimize transistor characteristics such as high transconductance, high breakdown voltage, fast operating speeds and device densities.
The LDD structure is a shallow, self-aligned n.sup.- or p.sup.- region formed between the MOSFET channel and the n.sup.+ or p.sup.+ source and drain diffusions. This structure increases breakdown voltage and reduces impact ionization and hot electron emission by spreading the high electric field at the drain pinchoff region into the n.sup.- or p.sup.- region.
The sidewall spacer is a layer of oxide which is selectively formed on the vertical edge of the gate electrode. This structure insulates the gate from the source/drain contact metallization and can be used as a dopant mask in a properly sequenced fabrication process to form the LDD structures in automatic alignment with the n.sup.+ and p.sup.+ source/drain diffusion regions.
Various approaches are summarized below for implementing LDD structures, gate electrode sidewall dielectric spacers, and low resistance gates and conductors and self-aligned contacts. The various documents discussed below are categorized based upon the perceived primary relevance of their disclosure.